NONBASETHRDENA=VALUE_0, STKALIGN=VALUE_0, USERSETMPEND=VALUE_0, DIV_0_TRP=VALUE_0, BFHFNMIGN=VALUE_0, UNALIGN_TRP=VALUE_0
Configuration and Control Register
| NONBASETHRDENA | Controls whether the processor can enter Thread mode with exceptions active 0 (VALUE_0): processor can enter Thread mode only when no exception is active 1 (VALUE_1): processor can enter Thread mode from any level under the control of an EXC_RETURN value |
| USERSETMPEND | Enables unprivileged software access to the STIR 0 (VALUE_0): disable 1 (VALUE_1): enable |
| UNALIGN_TRP | Enables unaligned access traps 0 (VALUE_0): do not trap unaligned halfword and word accesses 1 (VALUE_1): trap unaligned halfword and word accesses |
| DIV_0_TRP | Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 0 (VALUE_0): do not trap divide by 0 1 (VALUE_1): trap divide by 0 |
| BFHFNMIGN | Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 0 (VALUE_0): data bus faults caused by load and store instructions cause a lock-up 1 (VALUE_1): handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions |
| STKALIGN | Indicates stack alignment on exception entry 0 (VALUE_0): 4-byte aligned 1 (VALUE_1): 8-byte aligned |
| DC | Cache enable bit |
| IC | Instruction cache enable bi |
| BP | Branch prediction enable bi |